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| IS41LV44002B 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES * Extended Data-Out (EDO) Page Mode access cycle * TTL compatible inputs and outputs * Refresh Interval: * * * * * - 2,048 cycles/32 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden Single power supply: 3.3V 10% Byte Write and Byte Read operation via two CAS Industrial Temperature Range: -40C to +85C Lead-free available ISSI JULY 2006 (R) DESCRIPTION The ISSI IS41LV44002B is 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 2,048 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. These features make the IS41LV44002B ideally suited for high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral applications. The IS41LV44002B is packaged in a 24-pin 300-mil SOJ and 300-mil TSOP2 with JEDEC standard pinouts. PRODUCT SERIES OVERVIEW Part No. IS41LV44002B Refresh 2K Voltage 3.3V 10% KEY TIMING PARAMETERS Parameter RAS Access Time (tRAC) CAS Access Time (tCAC) Column Address Access Time (tAA) EDO Page Mode Cycle Time (tPC) Read/Write Cycle Time (tRC) -50 50 13 25 20 84 Unit ns ns ns ns ns PIN CONFIGURATION: 24-pin SOJ, TSOP2 VDD I/O0 I/O1 WE RAS NC A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GND I/O3 I/O2 CAS OE A9 A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A10 I/O0-3 WE OE RAS CAS VDD GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 1 IS41LV44002B FUNCTIONAL BLOCK DIAGRAM OE WE CAS CONTROL LOGIC WE CONTROL LOGICS OE CONTROL LOGIC ISSI (R) CAS CAS WE OE RAS RAS CLOCK GENERATOR DATA I/O BUS REFRESH COUNTER DATA I/O BUFFERS ROW DECODER RAS COLUMN DECODERS SENSE AMPLIFIERS I/O0-I/O3 MEMORY ARRAY 4,194,304 x 4 ADDRESS BUFFERS A0-A10 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write EDO Page-Mode Read 1st Cycle: 2nd Cycle: EDO Page-Mode Write 1st Cycle: 2nd Cycle: EDO Page-Mode 1st Cycle: Read-Write 2nd Cycle: Hidden Refresh Read Write(1) RAS-Only Refresh CBR Refresh Note: 1. EARLY WRITE only. RAS H L L L L L L L L L LHL LHL L HL CAS H L L L HL HL HL HL HL HL L L H L WE X H L HL H H L L HL HL H L X X OE X L X LH L L X X LH LH L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL NA/COL ROW/COL NA/COL ROW/COL NA/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT DIN DOUT, DIN DOUT DOUT DIN DIN DOUT, DIN DOUT, DIN DOUT DOUT High-Z High-Z 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B Functional Description The IS41LV44002B is a CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits. ISSI Auto Refresh Cycle (R) To retain data, 2,048 refresh cycles are required in each 32 ms period. There are two ways to refresh the memory: 1. By clocking each of the 2,048 row addresses (A0 through A10) with RAS at least once every 32 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Memory Cycle A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Power-On After application of the VDD supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VDD or be held at a valid VIH to avoid current surges. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 3 IS41LV44002B ABSOLUTE MAXIMUM RATINGS(1) Symbol VT VDD IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Rating -0.5 to +4.6 -0.5 to +4.6 50 1 -40 to +85 -55 to +125 Unit V V mA W C C ISSI (R) Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol VDD VIH VIL TA Parameter Supply Voltage Input High Voltage Input Low Voltage Commercial Ambient Temperature Industrial Ambient Temperature Min. 3.0 2.0 -0.3 0 -40 Typ. 3.3 -- -- -- -- Max. 3.6 VDD + 0.3 0.8 +70 +85 Unit V V V C C CAPACITANCE(1,2) Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A10 Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol IIL IIO VOH VOL ICC1 ICC2 ICC3 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Standby Current: TTL Standby Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: EDO Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR(2,3,5) Average Power Supply Current Test Condition Any input 0V VIN VDD Other inputs not under test = 0V Output is disabled (Hi-Z) 0V VOUT VDD IOH = -2.0 mA, VDD = 3.3V IOL = 2 mA, VDD = 3.3V RAS, CAS VIH RAS, CAS VDD - 0.2V RAS, CAS, Address Cycling, tRC = tRC (min.) RAS = VIL, CAS, Cycling tPC = tPC (min.) RAS Cycling, CAS VIH tRC = tRC (min.) RAS, CAS Cycling tRC = tRC (min.) -50 Speed Min. -5 -5 2.4 -- -- -- -- ISSI Max. 5 5 -- 0.4 2 0.5 120 A A V V (R) Unit mA mA mA ICC4 -50 -- 90 mA ICC5 -50 -- 120 mA ICC6 -50 -- 120 mA Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 5 IS41LV44002B AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -50 Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH tRHCP tCLZ tCRP tOD tOE tOED tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(23) CAS Precharge Time(9) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time RAS Hold Time from CAS Precharge CAS to Output in Low-Z(15, 24) CAS to RAS Precharge Time(21) Output Disable Time(19, 24) Output Enable Time(15, 16) Output Enable Data Delay (Write) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Min. 84 -- -- -- 50 30 8 9 38 12 0 8 0 8 30 10 25 5 8 30 0 5 3 -- 12 5 10 5 0 0 0 8 40 8 7 Max. -- 50 13 25 10K -- 10K -- -- 37 -- -- -- -- -- 25 -- -- -- -- -- -- 15 12 -- -- -- -- -- -- -- -- -- -- -- ISSI Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol tRWL tCWL tWCS tDHR tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCOH tOFF tWHZ tCSR tCHR tORD tREF tT Parameter Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time RAS Pulse Width in EDO Page Mode Access Time from CAS Precharge(15) EDO Page Mode READ-WRITE Cycle Time Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 24) Output Disable Delay from WE CAS Setup Time (CBR REFRESH)(20, 25) CAS Hold Time (CBR REFRESH)( 21, 25) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period 2,048 Cycles Transition Time (Rise or Fall)(2, 3) -50 Min. 13 8 0 39 15 8 0 8 108 64 26 39 20 50 -- 56 5 0 3 5 8 0 -- 1 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- 100K 30 -- -- 12 10 -- -- -- 32 50 ISSI Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns (R) AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF Input timing reference levels: VIH = 2.4V, VIL = 0.8V Output timing reference levels: VOH = 2.0V, VOL = 0.8V Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 7 IS41LV44002B ISSI (R) Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. Determined by falling edge of CAS. 21. Determined by rising edge of CAS. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. CAS must meet minimum pulse width. 24. The 3 ns minimum is a parameter guaranteed by design. 25. Enables on-chip refresh and address counters. 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B READ CYCLE ISSI tRC tRAS tRP (R) RAS tCSH tCRP tRCD tRSH tCAS tCLCH tRRH CAS tAR tASR tRAD tRAH tRAL tASC tCAH ADDRESS WE Row tRCS Column tRCH Row tAA tRAC tCAC tCLC tOFF(1) I/O Open tOE Valid Data tOD Open OE tOES Don't Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 9 IS41LV44002B EARLY WRITE CYCLE (OE = DON'T CARE) ISSI tRC tRAS tRP (R) RAS tCSH tCRP tRCD tRSH tCAS tCLCH CAS tAR tASR tRAD tRAH tASC tRAL tCAH tACH ADDRESS Row Column tCWL tRWL tWCR tWCS tWCH tWP Row WE tDHR tDS tDH I/O Valid Data Don't Care 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS ISSI tRP (R) RAS tCSH tCRP tRCD tRSH tCAS tCLCH CAS tAR tASR tRAD tRAH tRAL tASC tCAH tACH ADDRESS Row tRCS Column tRWD tCWD tAWD Row tCWL tRWL tWP WE tAA tRAC tCAC tCLZ tDS tDH I/O Open tOE Valid DOUT tOD Valid DIN Open tOEH OE Don't Care Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 11 IS41LV44002B EDO-PAGE-MODE READ CYCLE ISSI tRASP tRP (R) RAS tCSH tCRP tRCD tCAS, tCLCH tCP tPC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP CAS tAR tRAD tASR tASC tCAH tASC tCAH tASC tRAL tCAH ADDRESS Row tRAH tRCS Column Column Column tRCH Row tRRH WE tAA tRAC tCAC tCLZ tCAC tCOH tAA tCPA tCAC tCLZ tAA tCPA tOFF I/O Open tOE tOES Valid Data Valid Data tOEHC tOD tOES Valid Data tOE Open tOD OE tOEP Don't Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. 12 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B EDO-PAGE-MODE EARLY-WRITE CYCLE ISSI tRASP tRP (R) RAS tCSH tCRP tRCD tCAS, tCLCH tCP tPC tCAS, tCLCH tCP tRSH tCAS, tCLCH tACH tRAL tCAH tCP CAS tAR tRAD tASR tASC tACH tCAH tASC tACH tCAH tASC ADDRESS Row tRAH Column tCWL tWCS tWCH tWP Column tCWL tWCS tWCH tWP Column tCWL tWCS tWCH tWP Row WE tWCR tDHR tDS tDH tRWL tDS tDH tDS tDH I/O OE Valid Data Valid Data Valid Data Don't Care Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 13 IS41LV44002B ISSI tRASP tRP (R) EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) RAS tCSH tCRP tRCD tCAS, tCLCH tCP tPC / tPRWC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP CAS tASR tRAH tAR tRAD tASC tRAL tCAH tCAH tASC tCAH tASC ADDRESS Row tRWD tRCS Column tCWL tWP tAWD tCWD Column tCWL tWP tAWD tCWD Column tRWL tCWL tWP tAWD tCWD Row WE tAA tRAC tCAC tCLZ tDH tDS tAA tCPA tCAC tCLZ tDH tDS tAA tCPA tCAC tCLZ tDH tDS I/O Open tOE DOUT DIN tOD tOE DOUT DIN tOD tOE DOUT DIN tOD tOEH Open OE Don't Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. 14 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE) ISSI tRASP (R) tRP RAS tCSH tPC tCRP tRCD tCAS tCP tCAS tPC tCP tRSH tCAS tCP CAS tASR tRAH tAR tRAD tASC tACH tRAL tCAH tCAH tASC tCAH tASC ADDRESS Row tRCS Column (A) Column (B) tRCH tWCS Column (N) tWCH Row WE tAA tRAC tCAC tCPA tCAC tCOH tAA tWHZ tDS tDH I/O Open tOE Valid Data (A) Valid Data (B) DIN Open OE Don't Care Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 15 IS41LV44002B AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCAS tCP ISSI (R) CAS tAR tASR tRAD tRAH tASC tCAH tASC ADDRESS WE Row tRCS Column tRCH tRCS Column tAA tRAC tCAC tCLZ tWHZ tCLZ I/O Open tOE Valid Data Open tOD OE Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) RAS tRC tRAS tRP RAS tCRP tRPC CAS tASR tRAH ADDRESS I/O Row Open Row Don't Care 16 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 IS41LV44002B ISSI tRP tRAS tRP tRAS (R) CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) RAS tRPC tCP tCHR tCSR tRPC tCSR tCHR CAS I/O Open Don't Care HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tASR tRAD tRAH tASC tRAL tCAH ADDRESS Row Column tAA tRAC tCAC tCLZ tOFF(2) I/O Open tOE tORD Valid Data Open tOD OE Don't Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 17 IS41LV44002B ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) 50 50 50 50 Order Part No. IS41LV44002B-50J IS41LV44002B-50JL IS41LV44002B-50T IS41LV44002B-50TL Refresh 2K 2K 2K 2K Package 300-mil SOJ 300-mil SOJ, Lead-free 300-mil TSOP2 300-mil TSOP2, Lead-free ISSI (R) Industrial Range: -40C to +85C Speed (ns) 50 50 50 50 Order Part No. IS41LV44002B-50JI IS41LV44002B-50JLI IS41LV44002B-50TI IS41LV44002B-50TLI Refresh 2K 2K 2K 2K Package 300-mil SOJ 300-mil SOJ, Lead-free 300-mil TSOP2 300-mil TSOP2, Lead-free 18 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 07/05/06 PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J N ISSI (R) E1 E 1 D A SEATING PLANE B A2 C e b A1 E2 MILLIMETERS Sym. N0. Leads A A1 A2 b B C D E E1 E2 e -- 0.64 2.41 0.41 0.66 0.20 17.02 8.26 7.49 6.27 INCHES Min. Typ. Max. Min. Typ. Max. 24/26 -- -- -- -- -- -- -- -- -- -- 3.56 -- 2.67 0.51 0.81 0.25 17.27 8.76 7.75 7.29 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. -- 0.025 0.095 0.016 0.026 0.008 0.670 0.325 0.295 0.247 -- 0.140 -- -- -- -- -- -- -- -- -- -- 0.105 0.020 0.032 0.010 0.680 0.345 0.305 0.287 1.27 BSC 0.050 BSC Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 02/25/03 PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J ISSI (R) MILLIMETERS Sym. N0. Leads A A1 A2 b B C D E E1 E2 e -- 0.64 2.41 0.41 0.66 0.20 18.29 8.26 7.49 6.27 INCHES Min. Typ. Max. Sym. N0. Leads MILLIMETERS Min. Typ. Max. 32 -- 0.64 2.41 0.41 0.66 0.20 20.83 8.26 7.49 6.27 -- -- -- -- -- -- -- -- -- -- 3.56 -- 2.67 0.51 0.81 0.25 21.08 8.76 7.75 7.29 -- INCHES Min. Typ. Max. Min. Typ. Max. 28 -- -- -- -- -- -- -- -- -- -- 3.56 -- 2.67 0.51 0.81 0.25 18.54 8.76 7.75 7.29 -- 0.025 0.095 0.016 0.026 0.008 0.720 0.325 0.295 0.247 -- -- -- -- -- -- -- -- -- -- 0.140 -- 0.105 0.020 0.032 0.010 0.730 0.345 0.305 0.287 A A1 A2 b B C D E E1 E2 e -- -- -- -- -- -- -- -- -- -- 0.140 -- 0.105 0.020 0.032 0.010 0.830 0.345 0.305 0.287 0.025 0.095 0.016 0.026 0.008 0.820 0.325 0.295 0.247 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. D 02/25/03 PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) ISSI N/2+1 Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the (R) N E1 E package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1 D N/2 SEATING PLANE A e b L A1 c Plastic TSOP (T - Type II) (MS 25) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 24/26 A 1.20 0.0472 A1 0.05 0.15 0.002 0.0059 b 0.30 0.51 0.012 0.0201 c 0.12 0.21 0.005 0.0083 D 17.01 17.27 0.670 0.6899 E1 7.49 7.75 0.295 0.3051 e 1.27 BSC 0.050 BSC E 9.02 9.42 0.462 0.4701 L 0.40 0.60 0.016 0.0236 0 5 0 5 Plastic TSOP (T - Type II) (MS 24) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 40/44 A 1.20 0.0472 A1 0.05 0.15 0.002 0.0059 b 0.30 0.45 0.012 0.0157 c 0.12 0.21 0.005 0.0083 D 18.31 18.51 0.721 0.7287 E1 10.06 10.26 0.396 0.4040 e 0.80 BSC 0.031 BSC E 11.56 11.96 0.455 0.4709 L 0.40 0.60 0.016 0.0236 0 8 0 8 Plastic TSOP (T - Type II) (MS 24) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 44/50 A 1.20 0.0472 A1 0.05 0.15 0.002 0.0059 b 0.30 0.45 0.012 0.0157 c 0.12 0.21 0.005 0.0083 D 20.85 21.05 0.821 0.8287 E1 10.06 10.26 0.396 0.4040 e 0.80 BSC 0.031 BSC E 11.56 11.96 0.455 0.4709 L 0.40 0.60 0.016 0.0236 0 8 0 8 Integrated Silicon Solution, Inc. PK13197T40 Rev. C 08/013/99 |
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